1. Field of the Invention
The present invention relates generally to methods for forming vias through dielectric layers within microelectronic fabrications. More particularly, the present invention relates to methods for forming residue free vias through dielectric layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication device densities have increased and microelectronic fabrication device dimensions have decreased, it has become increasingly important within advanced microelectronic fabrications to form through dielectric layers within those advanced microelectronic fabrications vias, such as but not limited to contact vias and interconnection vias, of similarly commensurately decreased cross-sectional dimensions such that the vias may be formed through the dielectric layers within the advanced microelectronic fabrications without compromising the enhanced levels of integration desired within the advanced microelectronic fabrications.
A representative but by no means limiting integrated circuit microelectronic fabrication structure which illustrates one of several problems encountered when forming through a dielectric layer within an advanced integrated circuit microelectronic fabrication a contact via within the advanced integrated circuit microelectronic fabrication is illustrated by the schematic cross-sectional diagram of FIG. 1.
Shown in FIG. 1 is a semiconductor substrate 10 having formed therein an active region of the semiconductor substrate 10 defined by a pair of isolation regions 12a and 12b. Within and upon the active region of the semiconductor substrate 10 is formed an adjoining pair of field effect transistors (FETs) which share a source/drain region 20b formed within the active region of the semiconductor substrate 10. Employed in forming the adjoining pair of field effect transistors (FETs) is a pair of gate electrode stacks comprising: (1) a pair of gate dielectric layers 14a and 14b having formed and aligned thereupon; (2) a pair of gate electrode layers 16a and 16b which in turn have formed and aligned thereupon; (3) a pair of gate electrode dielectric cap layers 18a and 18b. In addition, there is formed within the semiconductor substrate 10 adjoining the pair of gate electrode stacks a series of source/drain regions 20a, 20b and 20c which are partially obscured by a series of dielectric spacer layers 22a, 22b, 22c and 22d formed adjoining the edges of the pair of gate electrode stacks. Finally, there is shown within FIG. 1 a blanket planarized premetal metal dielectric (PMD) layer 24 formed over the semiconductor substrate 10 including the adjoining pair of field effect transistors (FETs), where the blanket planarized pre-metal dielectric (PMD) layer 24 has formed thereupon a pair of patterned photoresist layers 26a and 26b. 
As is understood by a person skilled in the art, when the gate electrode stacks within FIG. 1 are formed with a first separation width W1 upon the active region of the semiconductor substrate 10 and the first separation width W1 approximates a minimum resolvable separation width achievable with an advanced photoexposure apparatus, a second separation width W2 of the pair of dielectric spacer layers 22b and 22c which is typically formed adjoining the pair of gate electrode stacks while employing a self aligned reactive ion etch (RIE) anisotropic etching method will of necessity be less than the minimum resolvable separation width achievable with the advanced photoexposure apparatus. Similarly, presuming that the same photoexposure apparatus is employed in forming the patterned photoresist layers 26a and 26b as is employed in defining the separation width W1 of the gate electrode stacks, the patterned photoresist layers 26a and 26b will also have a minimum separation width W1 which approximates the minimum separation width achievable with the advanced photoexposure apparatus. The patterned photoresist layers 26a and 26b will also have a registration tolerance variation (not shown in FIG. 1) which typically displaces the patterned photoresist layers 26a and 26b with respect to the gate electrode stacks.
In order to avoid forming an oversized and misaligned contact via through the portion of the blanket planarized pre-metal dielectric (PMD) layer 24 between the dielectric spacer layers 22b and 22c when accessing the source/drain region 20b within the active region of the semiconductor substrate 10, it is known in the art to employ a selective reactive ion etch (RIE) method which forms, in part, the contact via through the blanket planarized pre-metal dielectric (PMD) layer 24 in a self aligned fashion. The results of forming the contact via through such a selective reactive ion etch (RIE) method are illustrated in FIG. 2.
Shown in FIG. 2 is a schematic cross-sectional diagram of an integrated circuit microelectronic fabrication otherwise equivalent to the integrated circuit microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1, but wherein the contact via 27 has been etched while employing the selective reactive ion etch (RIE) method to expose the portion of the source/drain region 20b not obscured by the dielectric spacer layers 22b and 22c. As illustrated within FIG. 2, the selective reactive ion etch (RIE) method etches the dielectric material from which is formed the blanket planarized pre-metal dielectric (PMD) layer 24 but does not appreciably etch the dielectric material from which is formed the dielectric spacer layers 22b and 22c. Within typical integrated circuit microelectronic fabrications analogous or equivalent to the integrated circuit microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1 and FIG. 2, it is common in the art of integrated circuit fabrication to employ pre-metal dielectric (PMD) layers, such as the blanket planarized pre-metal dielectric (PMD) layer 24, formed from a silicon oxide dielectric material, while simultaneously employing dielectric spacer layers, such as the dielectric spacer layers 22b and 22c, formed from a silicon nitride dielectric material. When employing within an integrated circuit whose schematic cross-sectional diagram is analogous or equivalent to the integrated circuit whose schematic cross-sectional diagram is illustrated in FIG. 1 a pre-metal dielectric (PMD) layer formed of a silicon oxide dielectric material and a dielectric spacer layer formed of a silicon nitride material, it is possible to employ a selective reactive ion etch (RIE) method which typically employs a novel etchant gas composition comprising a fluorocarbon etchant gas to form with a substantial etch selectivity of the pre-metal dielectric (PMD) layer with respect to the dielectric spacer layer within the integrated circuit microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2.
While the use of a selective reactive ion etch (RIE) method employing a novel etchant gas composition comprising a perfluorocarbon etchant gas may readily provide from the integrated circuit microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1 the integrated circuit microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2 without compromising the width of the contact via 27 accessing the source/drain region 20b, under such circumstances the integrated circuit microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2 is typically not formed without problems. In particular, there is typically formed, as illustrated in FIG. 2, a fluorocarbon polymer residue layer 28 within the contact via 27 upon at least either the pair of patterned planarized pre-metal dielectric (PMD) layers 24a and 24b or the pair of dielectric spacer layers 22b and 22c. As is similarly illustrated in FIG. 2, the fluorocarbon polymer residue layer 28 within the contact via 27 is difficult to remove and typically remains within the contact via 27 even when exposed to methods and materials employed in stripping the patterned photoresist layers 26a and 26b to yield the integrated circuit microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2. Residue layers, such as the fluorocarbon polymer residue layer 28, formed within vias, such as the contact via 27 as illustrated in FIG. 2, are undesirable within advanced integrated circuit microelectronic fabrication since those residue layers typically provide high contact resistances to conductor stud layers formed within the vias.
It is thus towards the goal of forming within microelectronic fabrications including but not limited to integrated circuit microelectronic fabrications vias, such as but not limited to contact vias and interconnection vias, through dielectric layers within those microelectronic fabrications, while avoiding fluorocarbon polymer residue layers formed within those vias, that the present invention is generally directed.
Various disclosures may be found pertaining to microelectronic layer etch methods, such as microelectronic layer reactive ion etch (RIE) methods, for general etching of microelectronic layers within microelectronic fabrications, as well as for etching integrated circuit microelectronic layers when forming integrated circuit microelectronic structures within integrated circuit microelectronic fabrications.
For example, Egitto et al., in xe2x80x9cPlasma Etching Organic Materials. I. Polyimide in O2-CF4,xe2x80x9d disclose several characteristics of binary mixtures of oxygen and carbon tetrafluoride employed as etchant gas compositions when etching, while employing reactive ion etch (RIE) methods, microelectronic layers formed of polyimide materials. At carbon tetrafluoride concentrations of about 20 volume percent within a binary mixture with oxygen there is provided a reactive ion etch (RIE) etchant gas composition with optimally enhanced polyimide etch rate in comparison with a pure oxygen etchant gas composition within an otherwise equivalent reactive ion etch (RIE) plasma etch method.
In addition, Ryou, in U.S. Pat. No. 5,550,071 discloses an etching method for forming a conductor layer within a micro contact via accessing a semiconductor device electrode within a semiconductor integrated circuit microelectronic fabrication. The conductor layer and the micro contact via may be formed with a width narrower than an aperture within a patterned photoresist layer employed in defining the location and width of the conductor layer and micro contact via.
Finally, Koh et al., in U.S. Pat. No. 5,554,557 disclose an etching method for forming within an integrated circuit microelectronic fabrication a fence shaped capacitor having formed therein a capacitor node self aligned upon an integrated circuit microelectronic device electrode within the integrated circuit microelectronic fabrication. The method employs two sets of sidewall spacers in forming the fence shaped capacitor.
Desirable in the art are additional methods through which vias, such as but not limited to contact vias and interconnection vias, may be formed within microelectronic fabrications, such as but not limited to integrated circuit microelectronic fabrications. Particularly desirable in the art are additional methods through which vias, such as but not limited to contact vias and interconnection vias, may be formed in a self aligned fashion within microelectronic fabrications, such as but not limited to integrated circuit microelectronic fabrications. Most particularly desirable in the art are additional methods through which vias, such as but not limited to contact vias and interconnection vias, may be formed in a self aligned fashion through silicon oxide dielectric layers within microelectronic fabrications, such as but not limited to integrated circuit microelectronic fabrications, while: (1) employing reactive ion etch (RIE) methods which employ perfluorocarbon etchant gas compositions; and (2) avoiding fluorocarbon polymer residue layers formed within those vias.
It is towards the foregoing objects that the present invention is both generally and more specifically directed.
A first object of the present invention is to provide a method for forming a via, such as but not limited to a contact via or an interconnection via, through a dielectric layer within a microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where the via is formed employing a self aligned method through the dielectric layer within the microelectronic fabrication.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, where there is avoided when forming the via through the dielectric layer within the microelectronic fabrication while employing the self aligned method a fluorocarbon polymer residue layer formed within the via.
A fourth object of the present invention is to provide a method in accord with the first object of the present invention, the second object of the present invention or the third object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided a method for forming a via through a dielectric layer within a microelectronic fabrication. To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines within the microelectronic fabrication a contact region beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. The silicon oxide layer is then etched while employing a reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) a patterned silicon oxide layer having a via formed therethrough which exposes the contact region without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the patterned silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer while employing a down stream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and an oxidizing gas.
The method of the present invention also contemplates that there may in general be formed while employing the method of the present invention etched silicon oxide layers in the presence of silicon nitride layers while avoiding fluorocarbon polymer residue layers formed upon those etched silicon oxide layers and/or silicon nitride layers.
Similarly, the method of the present invention also contemplates in general a method for stripping fluorocarbon polymer residue layers from microelectronic layers including but not limited to silicon oxide layers and silicon nitride layers within microelectronic fabrications including but not limited to integrated circuit microelectronic fabrications.
In accord with the present invention, there is provided a self aligned method for forming a via through a dielectric layer within a microelectronic fabrication while avoiding a fluorocarbon polymer residue layer formed within the via through the dielectric layer. By: (1) employing within the method of the present invention a patterned silicon nitride layer which defines a contact region formed beneath the patterned silicon nitride layer; and (2) forming, while employing a reactive ion etch (RIE) method, through a silicon oxide layer formed upon the patterned silicon nitride layer a via accessing the contact region while not substantially etching the patterned silicon nitride layer, there is formed, while employing the present invention, a via through a self aligned method through a dielectric layer within a microelectronic fabrication. By employing within the method of the present invention a downstream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and an oxidizing gas to strip from the substrate the fluorocarbon polymer residue layer, there is removed, and therefore within the context of the present invention avoided, the fluorocarbon polymer residue layer when forming the via through the self aligned method through the dielectric layer. Within both the method of the present invention and the preferred embodiment of the method of the present invention removal of a fluorocarbon polymer residue layer is intended as synonymous with avoidance of a fluorocarbon polymer residue layer.
The method of the present invention is readily commercially implemented. The method of the present invention provides that there is employed within the method of the present invention: (1) a substrate having formed thereover a patterned silicon nitride layer which defines a contact region formed beneath the patterned silicon nitride layer; (2) a silicon oxide layer formed upon the patterned silicon nitride layer; (3) a reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas; and (4) a downstream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and an oxidizing gas. Methods and materials through which the foregoing layers, reactive ion etch (RIE) method and downstream plasma etch method may be employed within microelectronic fabrications are generally known within the art of microelectronic fabrication. Thus, the method of the present invention is readily commercially implemented.